1. Field of the Invention
The present invention relates to semiconductor circuits, and more particularly to charge coupled devices (CCDs) in which packets of charge created within a layer of semiconductor material are routed through the semiconductor layer in a desired manner by changing potential bias levels on electrodes mounted on an insulated layer above the semiconductor layer.
2. History of the Prior Art
Charge coupled devices (CCDs) comprise a well known form of semiconductor circuit for storing and processing data. In digital type CCDs binary values are commonly represented by the presence or absence of mobile charge carriers forming charge packets within the semiconductor material. The charge packets, which are stored in potential wells within the semiconductor material formed by application of an appropriate potential level to an electrode disposed over the potential well, are transferred to various other portions of the CCDs in desired fashion by changing the voltage levels applied to various electrodes overlaying the semiconductor material. Digital CCDs are capable of performing a variety of different digital or binary functions including functioning as digital memories and digital logic systems and subsystems.
As the complexity of CCD memories or digital logic functions increases, and as the density of CCDs increases, it becomes advantageous to be able to cross the CCD channels forming the signal paths. The operative link or connection between different elements may thereby be simplified or shortened, easing circuit layout problems and generally increasing density. A gating scheme is required to direct the charge packets or other signaling phenomena through desired portions of the various channels in desired directions and without interference with other charge packets at channel intersections or other common areas.
Channel crossover circuits have heretofore been unduly complex or otherwise impractical. One common technique employs an OR gate plus a channel divider. This approach is complex in terms of the components required and the controlling signals. Still other techniques are unduly complex because of a requirement for complex potential bias signals which are different from the data rate or phase relationship of the signals in the intersecting channels.
Heretofore, arrangements have been devised for controlling the flow of charge packets through intersecting channels as exemplified by U.S. Pat. No. 4,041,521 of Sunami et al and U.S. Pat. No. 4,051,505 of Krambeck et al. However, the Sunami et al and Krambeck et al arrangements relate to shift registers or other arrangements involving serial-to-parallel or parallel-to-serial operation within a matrix in which it is desired to store charge packets at various intersections of the matrix and thereafter transfer the stored packets in desired directions. The Sunami et al and Krambeck et al patents do not address themselves to the problem of a channel crossover circiut where charge packets in intersecting channels are not stored at the intersections but rather are transferred through the intersections substantially simultaneously and yet without interference with one another.
Accordingly, it is an object of the invention to provide a channel crossover circuit of relatively simple design and which is relatively easy to control.
It is a further object of the invention to provide a channel crossover circuit requiring only two intersecting channels having electrodes forming various storage and transfer gate areas therein.
It is a still further object of the invention to provide a channel crossover circuit of relatively simple design and which operates successfully using signals derived from or otherwise related to the data rate of the system.